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In the FIFO SRAM chain 10 shown in FIG.

The method defined in claim 51 further comprising after the addressing: charging the data signal lead to a logic 0 potential; addressing the data pass gate associated with a cell; and detecting the potential on the data signal lead to determine the state of the cell whose associated data pass gate has been enabled by the addressing following the charging.

The SRAM cells in the FIFO chains may also be used to control the connections made by the various interconnection conductor PLCs e.

A more detailed circuit diagram of a representative SRAM cell 120 is shown in FIG.

For example, programmable logic device 402 can be configured as a processor or controller that works in cooperation with processor 404.

3 is a simplified schematic diagram of a conventional FIFO SRAM chain.

standards and conformity assessment system, the American National Standards Institute ANSI empowers its members and constituents to strengthen the U.

PLCs 522 are provided for making programmable connections between selected intersecting conductors 520 and 540.

To program memory circuitry 110 all of pass gates 114 are disabled by logic 0 address signals ADDR-1, ADDR-2, etc.

Device 600 may be generally like the programmable logic devices shown in Freeman U.

Thereafter, to switch the SRAM cells 220 that need to be switched to logic 0, logic 1 is applied to DATA IN bar lead 212 and logic 0 is applied to the ADDR bar lead for each SRAM cell that needs to be switched.